1. Field of the Invention
The present invention relates to a clock control circuit built in a microcomputer comprising a main oscillator for a high speed operation and a sub oscillator for a low speed operation.
2. Description of Related Art
Some microcomputers, such as those having a timing function and those performing a low speed operation for saving a consumed power in addition to a high speed operation, conventionally include a sub oscillator for a low speed operation as well as a main clock oscillator for a high speed operation. The main clock oscillator generally has an oscillating frequency of 1 MHz or more, and tile sub oscillator has an oscillating frequency of approximately 32 KHz. In this type of microcomputer, a main clock generated by the main clock oscillator is generally used as a system clock in the high speed operation. In the low speed operation, it is not that a clock obtained by dividing the main clock is used but that, a sub clock generated by the sub oscillator is used instead. Further, the microcomputer has a function to stop generating the main clock in the low speed operation so as to decrease a power to be consumed.
Some of such microcomputers further have, for example, a wait function to further decrease the power consumption. The wait function is a function for suspending the supply of a clock signal to a CPU without halting the oscillator when a processing operation is not performed or when the CPU can be suspended (put in a wait state) except for a period when any external factor occurs. This function is used when the processing operation is conducted at predetermined time intervals or when the processing operation by the CPU is not required until any external factor such as external interrupt occurs. When this function is used, the power consumed by the microcomputer can be decreased by 20% through 40% as compared with when the CPU performs the ordinary processing operation.
By adopting both the sub clock and the wait function in this manner, the sub clock alone is generated and the generation of the main clock is suspended in the wait state when the operation of the CPU is halted, thereby stopping the supply of the system clock to tile CPU. Therefore, the power to be consumed can be further decreased. This mechanism is particularly significant in a product such as a portable telephone that uses a battery as a power supply and has to be kept with the power supply on for a long period of time.
A conventional clock control circuit for controlling this mechanism will now be described.
FIG. 1 is a block diagram showing the configuration of a conventional clock control circuit built in a microcomputer. As is shown in FIG. 1, reference numeral 1 denotes a main oscillator and reference numeral 2 denotes a sub oscillator. A main clock o.sub.M generated by a main oscillator 1 and a sub clock o.sub.S generated by a sub oscillator 2 are inputted to a clock selecting circuit 3. A signal M.sub.STP generated by main clock suspension selecting means 7 is inputted to one input terminal of an AND gate 71, and a control signal C.sub.SEL generated by system clock specifying means 6 is inputted to the other input terminal of the AND gate 71. The output of the AND gate 71 is supplied to the main oscillator 1. The control signal C.sub.SEL outputted by the system clock specifying means 6 is also supplied to the clock selecting circuit 3 via an inverter 61.
FIG. 2 is a diagram of the function block in the clock selecting circuit 3, and illustrates the clock selecting function of the clock selecting circuit. 3. A switch portion 35 includes NAND gates 31 and 32 and a NOR gate 33 (shown in FIG. 1). As described above, the sub clock o.sub.S is inputted to one input terminal of the NAND gate 31, and the control signal C.sub.SEL is inputted to the other input terminal thereof. The main clock o.sub.M is inputted to one input terminal of the NAND gate 32, and an inverted signal of the control signal C.sub.SEL is inputted to the other input terminal thereof. The outputs of the NAND gates 31 and 32 are supplied to the NOR gate 33, whose output is supplied to a clock buffer 34. In this manner, the switch portion 35 selects either the main clock o.sub.M or the sub clock o.sub.S, and the selected clock is amplified by the clock buffer 34 to be supplied to a second frequency divider circuit 4 as a system clock o.sub.0.
The main oscillator 1 and the sub oscillator 2 are actuated by connecting a predetermined vibrator, a capacity and the like between external terminals X.sub.IN and X.sub.OUT of the main oscillator 1 and between external terminals X.sub.CIN and X.sub.COUT of the sub oscillator 2, respectively.
The second frequency divider circuit 4 includes T flip-flops 41, 42, 43, . . . , etc. connected in series. The system clock o.sub.0 inputted to the second frequency divider circuit 4 is divided by the T flip-flops 41, 42, 43, . . . , etc., thereby being outputted as divided clocks o.sub.2.sub., o.sub.4, . . . , o.sub.n and o.sub.m, respectively.
The sub clock o.sub.S is inputted to a first frequency divider circuit 9 including a first T flip-flop 91 to be divided, and the obtained divided clock o.sub.S2 is supplied to a selection terminal of a switch 110. Also, the divided clocks o.sub.2, o.sub.4, . . . , o.sub.n and o.sub.m generated by the second frequency divider circuit 4 are supplied to the selection terminal of the switch 110. Through the switching function of the switch 110, the clock o.sub.S2 or the divided clocks o.sub.2, o.sub.4, . . . , o.sub.n and o.sub.m is inputted to a timer 10 for a clock.
A wait control circuit 5 receives various signals such as a wait instruction, an interrupt request, a reset request, a system clock o.sub.0 and a divided clock o.sub.2, thereby controlling the wait function. An output signal WT generated by the wait control circuit 5 is inputted to an inverter 51. An inverted signal of the signal WT generated by the inverter 51 is supplied to one input terminal of a NAND gate 52, the other input terminal of which receives the divided clock o.sub.2. A signal o.sub.CPU generated by the NAND gate 52 is supplied to a CPU (not shown).
FIG. 3 is a timing chart for the operation of the clock control circuit having the aforementioned configuration before, during and after the wait state. The operation in the wait state will be described referring to this timing chart and FIG. 1.
For transition to the wait state where the supply of the signal o.sub.CPU, that is, a clock source for the CPU, is suspended, the CPU activates the control signal C.sub.SEL generated by the system clock specifying means 6, thereby allowing the clock selecting circuit 3 to select the sub clock o.sub.S for the low speed operation. Therefore, the sub clock o.sub.S is used as the system clock o.sub.0. Then, the signal M.sub.STP generated by the main clock suspension selecting means 7 is activated, thereby suspending the oscillation of the main oscillator 1. At this point, the main clock o.sub.M undergoes a high to low transition. From this time on, as is shown in the timing chart of FIG. 3, the divided clocks o.sub.2, o.sub.4, . . . , o.sub.n and o.sub.m outputted by the second frequency divider circuit 4 and the signal o.sub.CPU are synchronized with the system clock o.sub.0, respectively. The divided clocks o.sub.2, o.sub.4, . . . , o.sub.n and o.sub.m work as clock sources for peripherals built in the microcomputer such as a timer, a serial I/O, an A/D converter and a watch dog timer.
Next, at a timing when the divided clock o.sub.2 is at a low level and the system clock o.sub.0 is at a fall, i.e., at a time t.sub.1 in FIG. 3, the CPU executes wait instruction, namely, the output signal WT of the wait control circuit 5 undergoes a low to high transition. As a result, the signal WT is inverted by the inverter 51 to be supplied to the AND gate 52, thereby making the signal o.sub.CPU undergo a high to low transition. Thus, the supply of the clock signal to the CPU is suspended, resulting in halting the CPU.
Even when the CPU is halted, however, the second frequency divider circuit 4 is operated to generate the divided clocks o.sub.2, o.sub.4, . . . , o.sub.n and o.sub.m. Therefore, the peripherals supplied with the divided clocks o.sub.2, o.sub.4, . . . , o.sub.n and o.sub.m are also operated even while the CPU is being suspended. Also, the first frequency divider circuit 4 is operated even when the CPU is suspended, and generates the divided clock o.sub.S2 by dividing the sub clock o.sub.S. Therefore, the timer 10 supplied with the divided clock o.sub.S2 is also operated.
In such a wait state, when an interrupt request is made due to, for example, the overflow of the timer 10, the wait control circuit 5 makes the output signal WT undergo a high to low transition at a timing when the divided clock o.sub.2 is at a low level and the system clock o.sub.0 is at, a fall, i.e., at a time t.sub.2 in FIG. 3. As a result, the wait state is released. From this time on, the supply of the signal o.sub.CPU is started, thereby resuming the operation of the CPU. The period between the times t.sub.1 and t.sub.2 is designated as a wait period.
Since the conventional clock control circuit works as described above, the clock selecting circuit 3 and tile second frequency divider circuit 4 are continued to be operated to supply the system clock o.sub.0 and the divided clocks o.sub.2, o.sub.4, . . . , o.sub.n and o.sub.m, even when the timer 10 alone is used for the purpose of releasing tile wait state and the other peripherals except for the timer 10 are not used at all before the release of the wait state. In such a case, the peripherals are regarded to waste the power.
In particular, since the NAND gate 33, the clock buffer 34, and the T flip-flops 41, 42, . . . , etc. are inherently designed to be suitable for a high speed operation, the transistors contained therein have large driving ability. Therefore, even when they are driven by using the sub clock o.sub.S for the low speed operation, a feedthrough current at a switching operation and a power consumed by a charge/discharge current for a load capacity cannot be negligible. For example, in a microcomputer manufactured by the Applicant, these transistors consume 20% through 30% of the entire power consumed in the wait state using the sub clock o.sub.S.
Further, the timer 10 is also operated by using, as the clock source, the divided clocks o.sub.2, o.sub.4, . . . , o.sub.n and o.sub.m obtained by dividing the main clock o.sub.M for the high speed operation. Therefore, a plurality of bits of counters are required to count, synchronously with one inputted clock, resulting in consuming a large power. Since the timer 10 for the clock using the sub clock o.sub.S as a clock source does not require a high frequency, a clock frequency of the timer 10 can be lower than the sub clock o.sub.S. Therefore, the divided clock o.sub.2S, that, is, a halved clock of the sub clock o.sub.S, is actually used.